SH7080 Datasheet, PDF (319/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
14, 13 WTRP[1:0] 00
R/W Number of Wait Cycles for Precharge Completion
Specify the number of minimum wait cycles to be
inserted for completion of precharge.
• From activation of auto precharge to ACTV
command issuance for the same bank.
• From issuance of PRE/PALL command to ACTV
command issuance for the same bank.
• From PALL command issuance to REF command
issuance in auto refresh.
• From PALL command issuance to SELF command
issuance in self-refresh.
The setting for areas 2 and 3 is common.
00: 0 cycle (No wait cycles)
01: 1 cycle
10: 2 cycles
11: 3 cycles
12

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
11, 10 WTRCD 01
[1:0]
R/W Number of Wait Cycles from ACTV Command to
READ(A)/WRIT(A) Command
Specify the number of minimum wait cycles from
issuing ACTV command to issuing READ(A)/WRIT(A)
command. The setting for areas 2 and 3 is common.
00: 0 cycle (No wait cycles)
01: 1 cycle
10: 2 cycles
11: 3 cycles
9

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 3.00 May 17, 2007 Page 261 of 1582
REJ09B0181-0300