SH7080 Datasheet, PDF (307/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 8)
CSnWCR specifies various wait cycles for memory accesses. The bit configuration of this register
varies as shown below according to the memory type (TYPE 2, TYPE 1, or TYPE 0) specified by
the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the target area.
CSnWCR should be modified only after CSnBCR setting is completed.
(1) Normal Space, SRAM with Byte Selection
• CS0WCR, CS1WCR, CS2WCR, CS3WCR, CS4WCR, CS5WCR, CS6WCR, CS7WCR,
CS8WCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
BAS
-
WW[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
SW[1:0]
WR[3:0]
WM
-
-
-
-
HW[1:0]
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R
R
R
R R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 21 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
20
BAS
0
R/W Byte Access Selection when SRAM with Byte Selection
is Used
Specifies the WRxx and RDWR signal timing when
SRAM interface with byte selection is used.
0: Asserts the WRxx signal at the read/write timing and
asserts the RDWR signal during the write access
cycle.
1: Asserts the WRxx signal during the read/write access
cycle and asserts the RDWR signal at the write
timing.
19

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 3.00 May 17, 2007 Page 249 of 1582
REJ09B0181-0300