SH7080 Datasheet, PDF (1039/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 20 Compare Match Timer (CMT)
20.4 Interrupts
20.4.1 CMT Interrupt Sources and DTC Activation
The CMT has channels and each of them to which a different vector address is allocated has
compare match interrupt. When both the interrupt request flag (CMF) and interrupt enable bit
(CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to
activate a CPU interrupt, the priority of channels can be changed by the interrupt controller
settings. For details, see section 6, Interrupt Controller (INTC).
The data transfer controller (DTC) can be activated by an interrupt request. In this case, the
priority between channels is fixed. See section 8, Data Transfer Controller (DTC), for details.
20.4.2 Timing of Setting Compare Match Flag
When CMCOR and CMCNT match, a compare match signal is generated and the CMF bit in
CMCSR is set to 1. The compare match signal is generated in the last cycle in which the values
match (when the CMCNT value is updated to H'0000). That is, after a match between CMCOR
and CMCNT, the compare match signal is not generated until the next CMCNT counter clock
input. Figure 20.4 shows the timing of CMF bit setting.
Peripheral operating
clock (Pφ)
Counter clock
(N + 1)th
clock
CMCNT
N
0
CMCOR
N
Compare match
signal
Figure 20.4 Timing of CMF Setting
20.4.3 Timing of Clearing Compare Match Flag
The CMF bit in CMCSR is cleared by reading 1 from this bit, then writing 0.
Rev. 3.00 May 17, 2007 Page 981 of 1582
REJ09B0181-0300