SH7080 Datasheet, PDF (367/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Table 9.21 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (2)-2
Setting
BSZ[1:0]
A2ROW[1:0]/ A2COL[1:0]/
A3ROW[1:0] A3COL[1:0]
11 (32 bits) 01 (12 bits)
10 (10 bits)
Output Pin of Row Address Column Address
This LSI
Output Cycle Output Cycle
SDRAM Pin
Function
A17
A27
A17
Unused
A16
A26
A16
A15
A25*²*³
A25*²*³
A14
A24*²
A24*²
A13 (BA1)
A12 (BA0)
Specifies bank
A13
A23
A13
A11
Address
A12
A22
L/H*¹
A10/AP
Specifies
address/precharge
A11
A21
A11
A9
Address
A10
A20
A10
A8
A9
A19
A9
A7
A8
A18
A8
A6
A7
A17
A7
A5
A6
A16
A6
A4
A5
A15
A5
A3
A4
A14
A4
A2
A3
A13
A3
A1
A2
A12
A2
A0
A1
A11
A1
Unused
A0
A10
A0
Example of connected memory
512-Mbit product (4 Mwords x 32 bits x 4 banks, column 10 bits product): 1
256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to
access mode.
2. Bank address specification
3. Only the RASL pin is asserted because the A25 pin specifies the bank address. RASU
is not asserted.
Rev. 3.00 May 17, 2007 Page 309 of 1582
REJ09B0181-0300