SH7080 Datasheet, PDF (1599/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page Revision (See Manual for Details)
4.4.1 Frequency Control Register 78,
(FRQCR)
79
Amended
Bit Bit Name Description
14 to IFC[2:0]
12
11 to BFC[2:0]
9
Internal Clock (Iφ) Frequency Division Ratio
Specify the division ratio of the internal clock (Iφ) frequency
with respect to the output frequency of PLL circuit. If a
prohibited value is specified, subsequent operation is not
guaranteed.
…….
100: ×1/8
Other than above: Setting prohibited
Bus Clock (Bφ) Frequency Division Ratio
Specify the division ratio of the bus clock (Bφ) frequency
with respect to the output frequency of PLL circuit. If a
prohibited value is specified, subsequent operation is not
guaranteed.
…….
100: ×1/8
Other than above: Setting prohibited
8 to 6 PFC[2:0] Peripheral Clock (Pφ) Frequency Division Ratio
Specify the division ratio of the peripheral clock (Pφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
…….
100: ×1/8
Other than above: Setting prohibited
5 to 3 MIFC[2:0] MTU2S Clock (MIφ) Frequency Division Ratio
Specify the division ratio of the MTU2S clock (MIφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
…….
100: ×1/8
Other than above: Setting prohibited
2 to 0 MPFC[2:0] MTU2 Clock (MPφ) Frequency Division Ratio
Specify the division ratio of the MTU2 clock (MPφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
…….
100: ×1/8
Other than above: Setting prohibited
Rev. 3.00 May 17, 2007 Page 1541 of 1582
REJ09B0181-0300