SH7080 Datasheet, PDF (765/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 13 Port Output Enable (POE)
13.4.1 Input Level Detection Operation
If the input conditions set by ICSR1 to ICSR3 occur on the POE0 to POE8 pins, the high-current
pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Note however,
that these high-current and MTU2 pins enter high-impedance state only when general input/output
function, MTU2 function, or MTU2S function is selected for these pins.
(1) Falling Edge Detection
When a change from a high to low level is input to the POE0 to POE8 pins, the high-current pins
and the pins for channel 0 of the MTU2 are placed in high-impedance state. Figure 13.2 shows a
sample timing after the level changes in input to the POE0 to POE8 pins until the respective pins
enter high-impedance state.
Pφ
POE input
Pφ rising edge
Falling edge detection
PE9/TIOC3B
High-impedance state*
Note: * The other high-current pins also enter the high-impedance state in the similar timing.
Figure 13.2 Falling Edge Detection
(2) Low-Level Detection
Figure 13.3 shows the low-level detection operation. Sixteen continuous low levels are sampled
with the sampling clock selected by ICSR1 to ICSR3. If even one high level is detected during this
interval, the low level is not accepted.
The timing when the high-current pins enter the high-impedance state after the sampling clock is
input is the same in both falling-edge detection and in low-level detection.
Rev. 3.00 May 17, 2007 Page 707 of 1582
REJ09B0181-0300