SH7080 Datasheet, PDF (435/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
The write buffer of the BSC functions in the same way for an access by the DMAC and DTC.
Accordingly, to perform dual address DMA transfers, the next read cycle is initiated before the
previous write cycle is completed. Note, however, that if both the DMA source and destination
addresses exist in external memory space, the next read cycle will not be initiated until the
previous write cycle is completed.
Since access cannot be performed correctly if any BSC register values are modified while the
write buffer is operating, do not modify BSC registers immediately after a write access. If the BSC
register need to be modified immediately after a write access, execute dummy read to confirm the
completion of the write access, then modify the BSC register.
Rev. 3.00 May 17, 2007 Page 377 of 1582
REJ09B0181-0300