HD6417706 Datasheet, PDF (95/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

From any state when
RESETP = 0
From any state but hardware standby
mode or bus-released state when RESETM = 0
Power-on reset
state
RESETP = 1
RESETP = 0
Manual reset
state
Reset state
RESETM = 1
Exception-handling state
Interrupt _{Bus-released state BuBsusrerqeuqceulBseetsuatsrcarlneecaqeruEianenxtscectererputpiot n}
End of exception
transition
processing
Bus _request
Program execution state
Bus
request
Bus
request
clearance
SLEEP
instruction
with STBY
bit cleared
SLEEP
instruction
with STBY
bit set
Interrupt
Sleep mode
CA = 1, RESETP=0
Hardware standby mode*
Software standby mode
Power-down state
Note: * The hardware standby mode is entered when the CA pin goes low level from any state.
Figure 2.6 Processor State Transitions
Rev. 4.00, 03/04, page 49 of 660