HD6417706 Datasheet, PDF(44/709 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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HD6417706 Datasheet, PDF (44/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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Section 14 Serial Communication Interface (SCI)

Table 14.1 SCI Pins ................................................................................................................ 351

Table 14.2 SCSMR Settings ................................................................................................... 366

Table 14.3 Bit Rates and SCBRR Settings in Asynchronous Mode ....................................... 367

Table 14.4 Bit Rates and SCBRR Settings in Clock Synchronous Mode............................... 369

Table 14.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator

synchronous Mode)............................................................................................... 370

Table 14.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode)............ 371

Table 14.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode) ... 371

Table 14.8 Serial Mode Register Settings and SCI Communication Formats ........................ 373

Table 14.9 SCSMR and SCSCR Settings and SCI Clock Source Selection ........................... 373

Table 14.10 Serial Communication Formats (Asynchronous Mode)........................................ 375

Table 14.11 Receive Error Conditions and SCI Operation....................................................... 381

Table 14.12 SCI Interrupt Sources............................................................................................ 396

Table 14.13 SCSSR Status Flags and Transfer of Receive Data .............................................. 397

Section 15 Smart Card Interface

Table 15.1 Pin Configuration.................................................................................................. 402

Table 15.2 Register Settings for the Smart Card Interface...................................................... 408

Table 15.3 Relationship of n to CKS1 and CKS0................................................................... 410

Table 15.4 Examples of Bit Rate B (Bit/s) for SCBRR Settings (n = 0) ................................ 410

Table 15.5 Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = 0) ................................ 411

Table 15.6 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) ..................... 411

Table 15.7 Register Set Values and SCKÏ Pin ....................................................................... 412

Table 15.8 Smart Card Mode Operating State and Interrupt Sources..................................... 416

Section 16 Serial Communication Interface with FIFO (SCIF)

Table 16.1 SCIF Pins .............................................................................................................. 425

Table 16.2 SCSMR2 Settings ................................................................................................. 439

Table 16.3 Bit Rates and SCBRR2 Settings ........................................................................... 440

Table 16.4 Maximum Bit Rates for Various Frequencies with

Baud Rate Generator (Asynchronous Mode)........................................................ 442

Table 16.5 Maximum Bit Rates during External Clock Input (Asynchronous Mode)............ 443

Table 16.6 SCSMR2 Settings and SCIF Communication Formats......................................... 446

Table 16.7 SCSCR2 and SCSCR2 Settings and SCIF Clock Source Selection...................... 447

Table 16.8 Serial Communication Formats ............................................................................ 447

Table 16.9 SCIF Interrupt Sources ......................................................................................... 456

Section 17 Pin Function Controller (PFC)

Table 17.1 List of Multiplexed Pins........................................................................................ 459

Section 18 I/O Ports

Table 18.1 Read/Write Operation of the Port A Data Register (PADR)................................. 480

Table 18.2 Read/Write Operation of the Port B Data Register (PBDR) ................................ 481

Table 18.3 Read/Write Operation of the Port C Data Register (PCDR) ................................. 483

Rev. 4.00, 03/04, page xliv of xlvi

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