HD6417706 Datasheet, PDF (385/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
2, 1
—
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
0
AF
0
R/W Alarm Flag
The AF flag is set to 1 when the alarm time set in an
alarm register (only registers with ENB bit set to 1)
matches the clock and calendar time. This flag is
cleared to 0 when 0 is written, but holds the previous
value when 1 is to be written.
0: Clock/calendar and alarm register have not matched
since last reset to 0.
[Clearing condition]
When 0 is written to AF
1: [Setting condition]
Clock/calendar and alarm register have matched
(only registers that ENB bit is 1)
13.3.16 RTC Control Register 2 (RCR2)
The RTC control register 2 (RCR2) is an 8-bit read/write register for periodic interrupt control, 30-
second adjustment ADJ, divider circuit RESET, and RTC count start/stop control. It is initialized
to H'09 by a power-on reset. It is initialized except for RTCEN and START by a manual reset. It is
not initialized in standby mode, and retains its contents.
Bit
Bit Name Initial Value R/W Description
7
PEF
0
R/W Periodic Interrupt Flag
Indicates interrupt generation with the period
designated by the PES bits. When set to 1, PEF
generates periodic interrupts.
0: Interrupts not generated with the period designated
by the PES bits.
[Clearing condition]
When 0 is written to PEF
1: Interrupts generated with the period designated by
the PES bits.
[Setting condition]
When 1 is written to PEF
Rev. 4.00, 03/04, page 339 of 660