HD6417706 Datasheet, PDF (90/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Notes: * The number of cycles until the sleep state is entered.
1. The table shows the minimum number of execution cycles. The actual number of
instruction execution cycles will increase in cases such as the followings:
a. When there is contention between an instruction fetch and data access
b. When the destination register in a load (memory-to-register) instruction is also
used by the next instruction
2. With the addressing modes using displacement (disp) listed below, the assembler
descriptions in this manual show the value before scaling (×1, ×2, or ×4) is performed.
This is done to clarify the operation of the chip. For the actual assembler descriptions,
refer to the individual assembler notation rules.
@ (disp:4, Rn) ;
Register-indirect with displacement
@ (disp:8, Rn) ;
GBR-indirect with displacement
@ (disp:8, PC) ;
PC-relative with displacement
disp:8, disp:12 ;
PC-relative
Rev. 4.00, 03/04, page 44 of 660