HD6417706 Datasheet, PDF (226/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 8.9 Area 0 Wait Control
WCR2's bits
Bit 2: Bit 1:
A0W2 A0W1
0
0
1
1
0
1
Bit 0:
A0W0
0
1
0
1
0
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
Ignored
2
Enable
1
Enable
2
Enable
2
Enable
3
Enable
3
Enable
4
Enable
4
Enable
4
Enable
6
Enable
6
Enable
8
Enable
8
Enable
10
Enable
10
Enable
8.4.5 Individual Memory Control Register (MCR)
The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS
and CAS timing and burst control for synchronous DRAM (areas 2 and 3), specifies address
multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without
external circuits.
The MCR is initialized to H'0000 by power-on resets, but is not initialized by manual resets or
standby mode. The bits TPC1, TPC0, RCD1, RCD0, TRWL1, TRWL0, TRAS1, TRAS0, RASD
and AMX3 to AMX0 are written to at the initialization after a power-on reset and are not then
modified again. When RFSH and RMODE are written to, write the same values to the other bits.
When using synchronous DRAM, do not access areas 2 and 3 until this register is initialized.
Rev. 4.00, 03/04, page 180 of 660