HD6417706 Datasheet, PDF (293/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

9.3.3 DMA Transfer Count Registers 0 to 3 (DMATCR_0 to DMATCR_3)
DMA transfer count registers 0 to 3 (DMATCR_0 to DMATCR_3) are 24-bit read/write registers
that specify the DMA transfer count (bytes, words, or longwords) in each channel. The number of
transfers is 1 when the setting is H'000001, and 16777216 (the maximum) when H'000000 is set.
During a DMA transfer, these registers indicate the remaining transfer count.
To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one.
Upper eight bits in DMATCR are reserved. These bits are always read as 0. The write value should
always be 0.
When using 16-byte transfer, an integral multiple of 4 (4n) must be set for the number of transfers
to ensure normal operation.
The initial value is undefined by resets. The previous value is held in standby mode.
Bit
31 to 24
23 to 0
Bit Name


Initial Value R/W

R

R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
24-bit register
9.3.4 DMA Channel Control Registers 0 to 3 (CHCR_0 to CHCR_3)
DMA channel control registers 0 to 3 (CHCR_0 to CHCR_3) are 32-bit read/write registers that
specifies operation mode, transfer method, or others in each channel.
These register values are initialized to 0s by resets. The previous value is held in standby mode.
When accessed in 16 bits, the other 16-bit data which has not been accessed is held.
Bit
31 to 21
Bit Name
—
Initial Value R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 4.00, 03/04, page 247 of 660