HD6417706 Datasheet, PDF (121/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Figure 3.12 shows the MMU exception signals in the data access mode.
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
ID EX MA WB
ID EX MA
ID EX
MMU exception handler
: Exception source stage
: Stage cancellation for instruction
that has begun execution
Handler transition
WB
processing
MA WB
NOP
NOP
IF ID EX MA WB
IF
ID
EX
MA
WB
NOP
= Instruction fetch
= Instruction decode
= Instruction execution
= Memory access
= Write back
= No operation
Figure 3.12 MMU Exception Signals in Data Access
Rev. 4.00, 03/04, page 75 of 660