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| HD6417706 Datasheet, PDF (631/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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24.3.4 Basic Timing
T1
T2
CKIO
A25 to A0
tAD tAS
CSn
RD/WR
tCSD1
tRWD
tRSD
RD
(read)
D31 to D0
(read)
WEn
(write)
D31 to D0
(write)
BS
DACKn
tWED
tWDD1
tBSD
tDAKD1
tAD
tCSD2
tAH
tRWH
tRDH1
tRWD
tRSD
tAH
tRWH
tRDS1
tRDH1
tWED
tAH
tRWH
tWDH3
tWDH1
tBSD
tDAKD2
Note:
tRDH1: Stipulated from the faster negate timing
tAH: Stipulated from the slower negate timing of
oCfSCnS, nRoDr,
RoDr WEn
Figure 24.16 Basic Bus Cycle (No Wait)
Rev. 4.00, 03/04, page 585 of 660
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