HD6417706 Datasheet, PDF (530/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

18.4.1 Register Description
Port D has the following register. Refer to section 23, List of Registers, for more details of the
addresses and access sizes.
• Port D data register (PDDR)
18.4.2 Port D Data Register (PDDR)
Port D data register (PDDR) is an 8-bit read/write register that stores data for pins PTD7 to PTD0.
PD7DT to PD0DT bit corresponds to PTD7 to PTD0 pin. When the pin function is general output
port, if the port is read, the value of the corresponding PDDR bit is returned directly. When the
function is general input port, if the port is read, the corresponding pin level is read.
PDDR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and
sleep mode, and in a manual reset.
Bit
Bit Name Initial Value R/W Description
7
PD7DT 0
R/W Table 18.4 shows the function of PDDR.
6
PD6DT 0
R/W
5
PD5DT 0
R/W
4
PD4DT 0
R/W
3
PD3DT 0
R/W
2
PD2DT 0
R/W
1
PD1DT 0
R/W
0
PD0DT 0
R/W
Table 18.4 Read/Write Operation of the Port D Data Register (PDDR)
PDnMD1 PDnMD0 Pin State
Read
Write
0
0
Other function PDDR value Value is written to PDDR, but does not affect
pin state.
1
Output
PDDR value Write value is output from pin.
1
0
Input (Pull-up Pin state
MOS: on)
Value is written to PDDR, but does not affect
pin state.
1
Input (Pull-up Pin state
Value is written to PDDR, but does not affect
MOS: off)
pin state.
(n = 0 to 7)
Rev. 4.00, 03/04, page 484 of 660