HD6417706 Datasheet, PDF (475/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

16.3.6 Serial Control Register 2 (SCSCR2)
The serial control register 2 (SCSCR2) operates the SCI transmitter/receiver, selects the serial
clock output in the asynchronous mode, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write the SCSCR2.
Bit
Bit Name Initial Value R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
Enables or disables the transmit-FIFO-data-empty
interrupt (TXI) requested when the serial transmit
data is transferred from the SCFTDR2 to SCTSR2,
and the quantity of data in the SCFTDR2 becomes
less than the specified number of transmission
triggers, and then the TDFE flag in the SCSSR2 is
set to1.
0: Transmit-FIFO-data-empty interrupt request
(TXI) is disabled.
Note: The TXI interrupt request can be cleared by
writing the greater quantity of transmit data
than the specified number of transmission
triggers to SCFTDR2 and by clearing TDFE
to 0 after reading 1 from TDFE, or can be
cleared by clearing TIE to 0.
1: Transmit-FIFO-data-empty interrupt request
(TXI) is enabled.
6
RIE
0
R/W Receive Interrupt Enable
Enables or disables the receive-data-full (RXI) and
receive-error (ERI) interrupts requested when the
serial receive data is transferred from the SCRSR2
to SCFRDR2, when the quantity of data in the
SCFRDR2 becomes more than the specified
number of receive triggers, and when the RDRF
flag of SCSSR2 is set to1.
0: Receive-data-full interrupt (RXI), receive-error
interrupt (ERI), and receive break interrupt (BRI)
requests are disabled.
Note: RXI and ERI interrupt requests can be
cleared by reading the DR, ER, or RDF flag after
it has been set to 1, then clearing the flag to 0,
or by clearing RIE to 0. At RDF, read 1 from the
RDF flag and clear it to 0, after reading the
received data from SCFRDR2 until the quantity
of received data becomes less than the
specified number of the receive triggers.
1: Receive-data-full interrupt (RXI) and receive-
error interrupt (ERI) requests are enabled.
Rev. 4.00, 03/04, page 429 of 660