HD6417706 Datasheet, PDF (180/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Interrupt
acceptance
Start of interrupt
processing
0.5 × Icyc
+ 0.5 × Bcyc
+ 3.5 × Pcyc
IRL
5 × Icyc
Instruction (instruction
replaced by interrupt
exception processing)
Overrun fetch
First instruction of interrupt
handler
IF ID EX EX EX EX
IF
IF ID EX
IF: Instruction fetch: Instruction is fetched from memory in which program is stored.
ID: Instruction decode: Fetched instruction is decoded.
EX: Instruction execution: Data operation and address calculation are performed in
accordance with result of decoding.
Figure 6.4 Example of Pipeline Operations when IRL Interrupt is Accepted
Rev. 4.00, 03/04, page 134 of 660