HD6417706 Datasheet, PDF (86/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 2.9 lists the branch instructions.
Table 2.9 Branch Instructions
Instruction
Operation
BF label If T = 0, disp × 2 + PC → PC;
if T = 1, nop (where label is
disp + PC)
BF/S label
Delayed branch, if T = 0,
disp × 2 + PC → PC;
if T = 1, nop
BT label Delayed branch, if T = 1,
disp × 2 + PC → PC;
if T = 0, nop
BT/S label
If T = 1, disp × 2 + PC → PC;
if T = 0, nop
BRA label
Delayed branch,
disp × 2 + PC → PC
BRAF Rm
Delayed branch,
Rm + PC → PC
BSR label
Delayed branch, PC → PR,
disp × 2 + PC → PC
BSRF Rm
Delayed branch, PC → PR,
Rm + PC → PC
JMP @Rm
Delayed branch, Rm → PC
JSR @Rm
Delayed branch, PC → PR,
Rm → PC
RTS
Delayed branch, PR → PC
Note:* One state when there is no branch.
Code
10001011dddddddd
10001111dddddddd
10001001dddddddd
10001101dddddddd
1010dddddddddddd
0000mmmm00100011
1011dddddddddddd
0000mmmm00000011
0100mmmm00101011
0100mmmm00001011
0000000000001011
Privileged
Mode
Cycles T Bit
—
3/1* —
—
2/1* —
—
3/1* —
—
2/1* —
—
2
—
—
2
—
—
2
—
—
2
—
—
2
—
—
2
—
—
2
—
Rev. 4.00, 03/04, page 40 of 660