HD6417706 Datasheet, PDF (473/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
7
—
0
R Reserved
This bit is always read 0. The write value should
always be 0.
6
CHR
0
R/W Character Length
Selects seven-bit or eight-bit data in the
asynchronous mode.
0: Eight-bit data.
1: Seven-bit data.
Note: When seven-bit data is selected, the MSB
(bit 7) in SCFTPR2 is not transmitted.
5
PE
0
R/W Parity Enable
Selects whether to add a parity bit to transmit data
and to check the parity of receive data.
0: Parity bit not added or checked.
1: Parity bit added and checked.
Note: When PE is set to 1, an even or odd parity
bit is added to transmit data, depending on the
parity mode (O/E) setting. Receive data parity is
checked according to the even/odd (O/E) mode
setting.
4
O/E
0
R/W Parity Mode
Selects even or odd parity when parity bits are
added and checked. The O/E setting is used only
when the PE is set to 1 to enable parity addition
and check. The O/E setting is ignored when parity
addition and check is disabled.
0: Even parity.
Note: If even parity is selected, the parity bit is
added to transmit data to make an even number
of 1s in the transmitted character and parity bit
combined. Receive data is checked to see if it
has an even number of 1s in the received
character and parity bit combined.
1: Odd parity.
Note: If odd parity is selected, the parity bit is
added to transmit data to make an odd number
of 1s in the transmitted character and parity bit
combined. Receive data is checked to see if it
has an odd number of 1s in the received
character and parity bit combined.
Rev. 4.00, 03/04, page 427 of 660