HD6417706 Datasheet, PDF (171/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
3
IRQ11S 0
R/W IRQ1 Sense Select
2
IRQ10S 0
R/W Select whether the interrupt signal to the IRQ1 pin is
detected at the rising edge, at the falling edge, or at
low level.
00: An interrupt request is detected at IRQ1 input
falling edge
01: An interrupt request is detected at IRQ1 input
rising edge
10: An interrupt request is detected at IRQ1 input
low level
11: Reserved (Setting prohibited)
1
IRQ01S 0
R/W IRQ0 Sense Select
0
IRQ00S 0
R/W Select whether the interrupt signal to the IRQ0 pin is
detected at the rising edge, at the falling edge, or at
low level.
00: An interrupt request is detected at IRQ0 input
falling edge
01: An interrupt request is detected at IRQ0 input
rising edge
10: An interrupt request is detected at IRQ0 input
low level
11: Reserved (Setting prohibited)
6.4.4 Interrupt Request Register 0 (IRR0)
The interrupt request register 0 (IRR0) is an 8-bit register that indicates interrupt requests from
external input pins IRQ0 to IRQ5.
When clearing IRQ5R to IRQ0R bit to 0, 0 should be written to the bit after the bit is set to 1 and
the contents of 1 are read. Only 0 can be written to IRQ5R to IRQ0R.
Bit
Bit Name Initial Value R/W Description
7, 6 —
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 4.00, 03/04, page 125 of 660