HD6417706 Datasheet, PDF (22/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

3.3.4 Page Management Information............................................................................ 64
3.4 MMU Functions................................................................................................................ 65
3.4.1 MMU Hardware Management ............................................................................. 65
3.4.2 MMU Software Management .............................................................................. 65
3.4.3 MMU Instruction (LDTLB)................................................................................. 66
3.4.4 Avoiding Synonym Problems .............................................................................. 67
3.5 MMU Exceptions.............................................................................................................. 69
3.5.1 TLB Miss Exception ............................................................................................ 69
3.5.2 TLB Protection Violation Exception ................................................................... 70
3.5.3 TLB Invalid Exception ........................................................................................ 71
3.5.4 Initial Page Write Exception ................................................................................ 72
3.5.5 Processing Flow in Event of MMU Exception
(Same Processing Flow for CPU Address Error)................................................. 74
3.6 Configuration of the Memory-Mapped TLB .................................................................... 76
3.6.1 Address Array ...................................................................................................... 76
3.6.2 Data Array............................................................................................................ 76
3.6.3 Usage Examples................................................................................................... 78
3.7 Usage Note........................................................................................................................ 78
3.7.1 Use of Instructions Manipulating MD and BL Bits in SR ................................... 78
3.7.2 Use of TLB .......................................................................................................... 79
Section 4 Exception Processing......................................................................... 81
4.1 Exception Processing Function ......................................................................................... 81
4.1.1 Exception Processing Flow.................................................................................. 81
4.1.2 Exception Processing Vector Addresses.............................................................. 82
4.1.3 Acceptance of Exceptions.................................................................................... 83
4.1.4 Exception Codes .................................................................................................. 85
4.1.5 Exception Request and BL Bit............................................................................. 86
4.1.6 Returning from Exception Processing ................................................................. 86
4.2 Register Description.......................................................................................................... 87
4.2.1 Exception Event Register (EXPEVT).................................................................. 87
4.2.2 Interrupt Event Register (INTEVT)..................................................................... 87
4.2.3 Interrupt Event Register 2 (INTEVT2)................................................................ 88
4.2.4 TRAPA Exception Register (TRA) ..................................................................... 88
4.3 Operation .......................................................................................................................... 89
4.3.1 Reset .................................................................................................................... 89
4.3.2 Interrupts.............................................................................................................. 89
4.3.3 General Exceptions .............................................................................................. 90
4.4 Individual Exception Operations....................................................................................... 90
4.4.1 Resets................................................................................................................... 90
4.4.2 General Exceptions .............................................................................................. 91
4.4.3 Interrupts.............................................................................................................. 94
4.5 Usage Note........................................................................................................................ 96
Rev. 4.00, 03/04, page xxii of xlvi