HD6417706 Datasheet, PDF (184/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

7.2.2 Break Address Mask Register A (BAMRA)
BAMRA is a 32-bit read/write register. BAMRA specifies bits masked in the break address
specified by BARA.
Bit
Bit Name Initial Value R/W
31 to 0 BAMA31 to All 0
R/W
BAMA0
Note: n = 31 to 0.
Description
Break Address Mask Bit
Specifies bits masked in the channel A break address
bits specified by BARA (BAA31 to BAA0).
0: Break address bit BAAn of channel A is included in
the break condition
1: Break address bit BAAn of channel A is masked and
is not included in the break condition
7.2.3 Break Bus Cycle Register A (BBRA)
Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the
break conditions of channel A.
Bit
15 to 8
Bit Name
—
Initial Value R/W
All 0
R
7
CDA1
0
R/W
6
CDA0
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
CPU Cycle/DMAC Cycle Select A
Selects the CPU cycle or DMAC cycle as the bus
cycle of the channel A break condition.
00: Condition comparison is not performed
X1: The break condition is the CPU cycle
10: The break condition is the DMAC cycle
Rev. 4.00, 03/04, page 138 of 660