HD6417706 Datasheet, PDF (12/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Item
9.3 Register Description
Page
246
9.5.3 Operation
285
Figure 9.27 Counter
Operation
10.1 Feature
292
Figure 10.1 Block Diagram of
Clock Pulse Generator
Revision (See Manual for Details)
Description added
Channel 3
• DMA source address register 3 (SAR3)
• DMA destination address register 3 (DAR3)
• DMA transfer count register 3 (DMATCR3)
• DMA channel control register 3 (CHCR3)
Any Channel
• DMA operation register (DMAOR)
Figure 9.27 amended
(Before) CMCNT0 value → (After) CMCNT value
(Before) CMCOR0 → (After) CMCOR
Figure 10.1 amended
Clock pulse generator
CAP1
CKIO
Cycle = Bcyc
CAP2
XTAL
EXTAL
Crystal
oscillator
PLL circuit 1
(× 1, 2, 3, 4)
PLL circuit 2
(× 1, 4)
Divider 1
×1
× 1/2
× 1/3
× 1/4
Divider 2
×1
× 1/2
× 1/3
× 1/4
× 1/6
Internal
clock (Iφ)
Cycle = Icyc
Peripheral
clock (Pφ)
Cycle = Pcyc
Bus clock (Bφ)
Cycle = Bcyc
293 5. description amended
5. Divider 2: Divider 2 generates a clock at the operating frequency
used by the bus clock (Bφ) and peripheral clock (Pφ). The
operating frequency of the peripheral clock can be 1, 1/2, 1/3, 1/4,
or 1/6 times the output frequency of PLL Circuit 1, as long as it
stays at or below the clock frequency of the CKIO pin. The
division ratio is set in the frequency control register.
Rev. 4.00, 03/04, page xii of xlvi