HD6417706 Datasheet, PDF (221/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
13
A6IW1
1
R/W Area 6 Intercycle Idle Specification
12
A6IW0
1
R/W Specify the number of idles inserted between bus
cycles when switching between physical space area 6
to another space or between a read access to a write
access in the same physical space.
00: 1 idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 3 idle cycles inserted
11
A5IW1
1
R/W Area 5 Intercycle Idle Specification
10
A5IW0
1
R/W Specify the number of idles inserted between bus
cycles when switching between physical space area 5
to another space or between a read access to a write
access in the same physical space.
00: 1 idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 3 idle cycles inserted
9
A4IW1
1
R/W Area 4 Intercycle Idle Specification
8
A4IW0
1
R/W Specify the number of idles inserted between bus
cycles when switching between physical space area 4
to another space or between a read access to a write
access in the same physical space.
00: 1 idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 3 idle cycles inserted
7
A3IW1
1
R/W Area 3 Intercycle Idle Specification
6
A3IW0
1
R/W Specify the number of idles inserted between bus
cycles when switching between physical space area 3
to another space or between a read access to a write
access in the same physical space.
00: 1 idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 3 idle cycles inserted
Rev. 4.00, 03/04, page 175 of 660