HD6417706 Datasheet, PDF (427/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

In receiving, the SCI operates as follows:
1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes
internally and starts receiving.
2. Receive data is stored into the SCRSR in order from the LSB to the MSB.
3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following
checks:
a. Parity check: The number of 1s in the receive data must match the even or odd parity
setting of the O/E bit in the SCSMR.
b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit
is checked.
c. Status check: RDRF must be 0 so that receive data can be loaded from the SCRSR into the
SCRDR.
If these checks all pass, the SCI sets RDRF to 1 and stores the received data in the SCRDR.
If one of the checks fails (receive error), the SCI operates as indicated in table 14.11.
Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1.
Be sure to clear the error flags.
4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the
SCSCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER,
PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCSCR is
also set to 1, the SCI requests a receive-error interrupt (ERI).
Table 14.11 Receive Error Conditions and SCI Operation
Receive Error
Overrun error
Framing error
Parity error
Abbreviation
ORER
FER
PER
Condition
Data Transfer
Receiving of next data ends while Receive data not loaded
RDRF is still set to 1 in SCSSR from SCRSR into
SCRDR
Stop bit is 0
Receive data loaded from
SCRSR into SCRDR
Parity of receive data differs from Receive data loaded from
even/odd parity setting in SCSMR SCRSR into SCRDR
Rev. 4.00, 03/04, page 381 of 660