HD6417706 Datasheet, PDF (626/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

24.3.2 Control Signal Timing
Table 24.6 Control Signal Timing
Item
Symbol
Min
Max
Unit Figure
RESETP pulse width
RESETP setup time*¹
tRESPW
20*³
—
tRESPS
20
—
tcyc
24.11,
ns
24.12
RESETP hold time
RESETM pulse width
tRESPH
2
—
tRESMW
12*⁴
—
ns
tcyc
RESETM setup time
tRESMS
6
—
ns
RESETM hold time
tRESMH
34
—
ns
BREQ setup time
tBREQS
6
—
ns
24.14
BREQ hold time
NMI setup time *¹
tBREQH
4
—
ns
tNMIS
10
—
ns
24.12,
NMI hold time
IRQ5 to IRQ0 setup time *¹
tNMIH
4
—
ns
24.13
tIRQS
10
—
ns
IRQ5 to IRQ0 hold time
tIRQH
4
—
ns
IRQOUT delay time
tIRQOD
—
10
ns
BACK delay time
tBACKD
—
10
ns
24.14,
STATUS1, STATUS0 delay time
tSTD
—
10
ns
24.15
Bus tri-state delay time 1
tBOFF1
0
15
ns
Bus tri-state delay time 2
tBOFF2
0
15
ns
Bus buffer-on time 1
tBON1
0
15
ns
Bus buffer-on time 2
tBON2
0
15
ns
Notes: 1. RESETP, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected at the
clock fall when the setup shown is used. When the setup cannot be used, detection
can be delayed until the next clock falls.
2. The upper limit of the external bus clock is 66 MHz.
3. In the standby mode, when XTAL oscillation continues, tRESPn = tOSC1 (100µs), when
XTAL oscillation stops, tRESPW = tOSC2 (10 ms). In the sleep mode, tRESPW = tPLL1 (100
µs).
When the clock multiplication ratio is changed, tRESPW = tPLL1 (100 µs).
4. In the standby mode, tRESMW = tOSC2 (10 ms). In the sleep mode, RESETM must be kept
low until STATUS (0-1) changes to reset (HH). When the clock multiplication ratio is
changed, RESETM must be kept low until STATUS (0-1) changes to reset (HH).
Rev. 4.00, 03/04, page 580 of 660