HD6417706 Datasheet, PDF(431/709 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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HD6417706 Datasheet, PDF (431/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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In transmitting serial data, the SCI operates as follows:

1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes

that the SCTDR contains new data, and loads this data from the SCTDR into the SCTSR.

2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and

starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCSCR is set to

1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is

transmitted in the following order from the TxD0 pin:

A. Start bit: One 0 bit is output.

B. Transmit data: Seven or eight bits are output, LSB first.

C. Multiprocessor bit: One multiprocessor bit (MPBT value) is output.

D. Stop bit: One or two 1 bits (stop bits) are output.

E. Marking: Output of 1 bits continues until the start bit of the next transmit data.

3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data

from the SCTDR into the SCTSR, outputs the stop bit, then begins serial transmission of the

next frame. If TDRE is 1, the SCI sets the TEND bit in the SCSSR to 1, outputs the stop bit,

then continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit

(TEIE) in the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.

Figure 14.14 shows SCI transmission in the multiprocessor format.

1

Serial

data

Start

bit

Data

Multi-

processor

bit Stop

bit

Start

bit

0 D0 D1

D 7 0/1 1 0 D 0

Data

Multi-

processor

bit Stop

bit

D1

D 7 0/1 1

1

Idling

(marking)

TDRE

TEND

TXI interrupt

request

generated

Writes data to

TDR with the TXI

interrupt pro-

cessing routine and

clears TDRE bit to 0

TXI interrupt

request

generated

1 frame

TEI interrupt

request

generated

Example: 8-bit data with multiprocessor bit and one stop bit

Figure 14.14 SCI Multiprocessor Transmit Operation

Rev. 4.00, 03/04, page 385 of 660

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