HD6417706 Datasheet, PDF (550/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

When the mode or analog input channel must be switched during A/D conversion, to prevent
incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making
the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be
set at the same time as the mode or channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next.
Figure 19.5 shows a timing diagram for this example.
1. Single mode is selected (MULTI = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 =
1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time
the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt processing routine starts.
5. The routine reads ADCSR, then writes 0 in the ADF flag.
6. The routine reads and processes the conversion result (ADDRB = 0).
7. Execution of the A/D interrupt processing routine ends. Then, when the ADST bit is set to 1,
A/D conversion starts to execute 2 to 7 above.
ADIE
Set*
Set*
ADST A/D conversion starts
ADF
Channel 0 (AN0)
operating
Channel 1 (AN1)
operating
Channel 2 (AN2)
operating
Channel 3 (AN3)
operating
ADDRA
Waiting
Waiting
A/D conversion 1
Waiting
Waiting
ADDRB
Clear*
Set*
Clear
Waiting
A/D conversion result 2
Waiting
Read result
A/D conversion result 1
Read result
A/D conversion result 2
ADDRC
ADDRD
Note: * Downward arrows (↓) indicate instruction execution.
Figure 19.5 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Rev. 4.00, 03/04, page 504 of 660