HD6417706 Datasheet, PDF (485/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

16.3.8 Bit Rate Register 2 (SCBRR2)
The bit rate register 2 (SCBRR2) is an eight-bit register that, together with the baud rate generator
clock source selected by the CKS1 and CKS0 bits in the SCSMR2, determines the serial
transmit/receive bit rate.
The CPU can always read and write the SCBRR2. The SCBRR2 is initialized to H'FF by a reset or
in module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
The SCBRR2 setting is calculated as follows:
Asynchronous mode: N =
Pφ
64 × 2^{2n – 1} × B
× 10⁶ – 1
B: Bit rate (bit/s)
N: SCBRR2 setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 16.2.)
Table 16.2 SCSMR2 Settings
n
Clock Source
CKS1
0
Pφ
0
1
Pφ/4
0
2
Pφ/16
1
3
Pφ/64
1
Note: Find the bit rate error by the following formula:
SCSMR2 Settings
CKS0
0
1
0
1
Error (%) =
Pφ × 10⁶
– 1 × 100
(N+1) × 64 × 2^2n–1 × B
Rev. 4.00, 03/04, page 439 of 660