HD6417706 Datasheet, PDF (532/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
7
PE7DT 0
R/W Table 18.5 shows the function of PEDR.
6
PE6DT 0
R/W
5
PE5DT 0
R/W
4
PE4DT 0
R/W
3
PE3DT 0
R/W
2
PE2DT 0
R/W
1
PE1DT 0
R/W
0
PE0DT 0
R/W
Table 18.5 Read/Write Operation of the Port E Data Register (PEDR)
PEnMD1 PEnMD0 Pin State
Read
Write
0
0
Other function PEDR value Value is written to PEDR, but does not affect
pin state.
1
Output
PEDR value Write value is output from pin.
1
0
Input (Pull-up Pin state
MOS: on)
Value is written to PEDR, but does not affect
pin state.
1
Input (Pull-up Pin state
Value is written to PEDR, but does not affect
MOS: off)
pin state.
(n = 0 to 7)
18.6 Port F
Port F is a 7-bit input/output port with the pin configuration shown in figure 18.6. Each pin has an
input pull-up MOS, which is controlled by Port F Control Register (PFCR) in PFC.
Port F
PTF6 (I/O) /
(output)
PTF5 (I/O) / TDO (output)
PTF4 (I/O) / AUDSYNC (output)
PTF3 (I/O) / AUDATA3 (I/O)
PTF2 (I/O) / AUDATA2 (I/O)
PTF1 (I/O) / AUDATA1 (I/O)
PTF0 (I/O) / AUDATA0 (I/O)
Figure 18.6 Port F
Rev. 4.00, 03/04, page 486 of 660