HD6417706 Datasheet, PDF (461/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

1. Initialize the smart card interface mode as described above in Initialization and in figure 15.5.
2. Check that the ORER and PER flags in SCSSR are cleared to 0. If either flag is set, clear both
to 0 after performing the appropriate error processing procedures.
3. Repeat steps 2 and 3 until the RDRF flag is set to 1.
4. Read the receive data from SCRDR.
5. To receive more data, clear the RDRF flag to 0 and return to step 2.
6. To end reception, clear the RE bit to 0.
This processing can be interrupted. When the RIE bit is set to 1 and interrupt requests are enabled,
a receive-data-full interrupt (RXI) will be requested when the RDRF flag is set to 1 at the end of
the reception. When an error occurs during reception and either the ORER or PER flag is set to 1,
a communication error interrupt (ERI) will be requested. See Interrupt Operation below for more
information.
The received data will be transferred to SCRDR even when a parity error occurs during reception
and PER is set to 1, so this data can still be read.
Start
Initialize
Start reception
ORER = 0 or PER = 0?
No
Yes
No
RDRF = 1?
Yes
Write receive data from
SCRDR and clear
RDRF flag in SCSSR to 0
No
All data received?
Yes
Clear RE bit in SCSCR to 0
Error processing
End reception
Figure 15.7 Reception Flowchart (Example)
Rev. 4.00, 03/04, page 415 of 660