HD6417706 Datasheet, PDF (374/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

13.3.1 64-Hz Counter (R64CNT)
The 64-Hz counter (R64CNT) is an 8-bit read-only register that indicates the state of the RTC
divider circuit between 64 Hz and 1 Hz.
R64CNT is reset to H'00 by setting the RESET bit in RCR2 or the ADJ bit in RCR2 to 1.
R64CNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit
7
6 to 0
Bit Name


Initial Value R/W
0
R

R
Description
Always read as 0.
64Hz counter
Each bit (bits 6 to 0) indicates the state of the RTC
divider circuit between 64 and 1Hz.
Bit
Frequency
6:
1Hz
5:
2Hz
4:
4Hz
3:
8Hz
2:
16Hz
1:
32Hz
0:
64Hz
13.3.2 Second Counter (RSECCNT)
The second counter (RSECCNT) is an 8-bit read/write register used for setting/counting in the
BCD-coded second section of the RTC. The count operation is performed by a carry for each
second of the 64-Hz counter.
The range of second can be set is 00 to 59 (decimal). Errant operation will result if any other value
is set. Carry out write processing after halting the count operation with the START bit in RCR2.
RSECCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit
7
6 to 4
3 to 0
Bit Name



Initial Value R/W
0
R

R/W

R/W
Description
Always read as 0.
Counter for 10-unit of second in the BCD-code. The
range can be set from 0 to 5 (decimal).
Counter for 1-unit of second in the BCD-code. The
range can be set from 0 to 9 (decimal).
Rev. 4.00, 03/04, page 328 of 660