HD6417706 Datasheet, PDF (621/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Item
Symbol Min
CKIO clock input frequency
fCKI
25
CKIO clock input cycle time
tCKIcyc
15
CKIO clock input low pulse width
tCKIL
1.5
CKIO clock input high pulse width
tCKIH
1.5
CKIO clock input rise time
tCKIR
—
CKIO clock input fall time
tCKIF
—
CKIO clock output frequency
fOP
25
CKIO clock output cycle time
tcyc
15
CKIO clock output low pulse width
tCKOL
3
CKIO clock output high pulse width
tCKOH
3
CKIO clock output rise time
tCKOR
—
CKIO clock output fall time
tCKOF
—
Power-on oscillation settling time
tOSC1
10
RESETP setup time (at the power-on or tRESPS
20
at the release from standby mode)
RESETM setup time (at the release from tRESMS 0
standby mode)
RESETP assert time (at the power-on or tRESPW 20
at the release from standby mode)
RESETM assert time (at the release tRESMW 20
from standby mode)
Standby return oscillation settling time 1 tOSC2
10
Standby return oscillation settling time 2 tOSC3
10
Standby return oscillation settling time 3 tOSC4
11
PLL synchronization settling time 1
tPLL1
100
(at the release from standby mode)
PLL synchronization settling time 2
tPLL2
100
(at the modification of multiplication rate)
IRQ/IRL interrupt determination time tIRLSTB 100
(RTC is used in the standby mode)
Max Unit
66.67 MHz
40 ns
— ns
— ns
6
ns
6
ns
66.67 MHz
40 ns
— ns
— ns
5
ns
5
ns
— ms
— ns
Figure
24.2
24.3
24.4
24.4, 24.5
— ns
— tcyc
— tcyc
— ms 24.5
— ms 24.6
— ms 24.7
— µs 24.8, 24.9
— µs 24.10
— µs 24.10
Rev. 4.00, 03/04, page 575 of 660