HD6417706 Datasheet, PDF (402/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
6
RIE
0
R/W Receive Interrupt Enable
Enables or disables the receive-data-full interrupt
(RXI) request when the serial receive data is
transferred from SCRSR to SCRDR and the
receive data register full bit (RDRF) in SCSSR is
set to 1. It also enables or disables receive-error
interrupt (ERI) requests.
0: Receive-data-full interrupt (RXI) and receive-
error interrupt (ERI) requests are disabled
Note: RXI and ERI interrupt requests can be
cleared by reading 1 from the RDRF flag or
error flag (FER, PER, or ORER) then clearing
the flag to 0, or by clearing RIE to 0.
1: Receive-data-full interrupt (RXI) and receive-
error interrupt (ERI) requests are enabled
5
TE
0
R/W Transmit Enable
Enables or disables the SCI serial transmitter.
0: Transmission disabled
Note: The TDRE in SCSSR is fixed to 1.
1: Transmission enabled
Note: Serial transmission starts when TDRE bit
in SCSSR is cleared to 0 after writing of transmit
data into the SCTDR. Specify the transmit
format to the SCSMR before setting TE to 1.
4
RE
0
R/W Receive Enable
Enables or disables the SCI serial receiver.
0: Reception disabled
Note: Clearing RE to 0 does not affect the
receive flags (RDRF, FER, PER, ORER). These
flags retain their previous values.
1: Reception enabled
Note: Serial reception starts when a start bit is
detected in the asynchronous mode, or
synchronous clock input is detected in the clock
synchronous mode. Specify the receive format
to the SCSMR before setting RE to 1.
Rev. 4.00, 03/04, page 356 of 660