HD6417706 Datasheet, PDF (103/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

3.2.2 Page Table Entry Register Low (PTEL)
The page table entry register low register (PTEL) is used to store the physical page number and
page management information to be recorded in the TLB by the LDTLB instruction. The contents
of this register are only modified by a software command.
Bit
31 to 10
9
8
7
6, 5
4
3
2
1
0
Bit Name
PPN

V

PR
SZ
C
D
SH

Initial Value R/W

R/W
0
R

R/W
0
R

R/W

R/W

R/W

R/W

R/W
0
R
Description
Physical page number
Page management information
Refer to section 3.3 TLB Functions.
3.2.3 The Translation Table Base Register (TTB)
The translation table base register (TTB) is a 32-bit register. TTB is used to store the base address
of the current page table. The contents of this register are only modified in response to a software
command. TTB is available to use by software for general purposes.
3.2.4 The TLB Exception Address Register (TEA)
The TLB exception address register (TEA) is a 32-bit register. TEA is used to store the virtual
address corresponding to a MMU or CPU address error exception after these exceptions has
occurred. This value remains valid until the next exception or interrupt occurs.
Rev. 4.00, 03/04, page 57 of 660