HD6417706 Datasheet, PDF (451/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
3
PER
0
R/(W)* Parity error
2
TEND
1
R
Transmission end
1
MPB
0
R
Multiprocessor bit
0
MPBT
0
R/W Multiprocessor bit transfer
These bits have the same function as in the ordinary
SCI. See section 14, Serial Communication Interface
(SCI), for more information. The setting conditions
for bit 2, the transmit end bit (TEND), are changed
as follows.
0: Transmission is in progress.
[Clearing condition]
TDRE is read as 1, then written to with 0.
1: End of transmission.
[Setting conditions]
1. The chip is reset or enters standby mode.
2. TE bit in SCSCR is 0 and the FER/ERS bit is
also 0.
3. C/A bit in SCSMR is 0, and TDRE = 1 and
FER/ERS = 0 (normal transmission) 2.5 etu
after a one-byte serial character is transmitted.
4. C/A bit in SCSMR is 1, and TDRE = 1 and
FER/ERS = 0 (normal transmission) 1.0 etu
after a one-byte serial character is transmitted.
Note: etu is an abbreviation of elementary time unit,
which is the period for the transfer of 1 bit.
Note: * Only 0 can be written, to clear the flag.
Rev. 4.00, 03/04, page 405 of 660