HD6417706 Datasheet, PDF (218/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
1
A5PCM 0
R/W Area 5 Bus Type
Designates whether to access physical space area 5
as PCMCIA space.
0: Access physical space area 5 as ordinary memory
1: Access physical space area 5 as PCMCIA space
0
A6PCM 0
R/W Area 6 Bus Type
Designates whether to access physical space area 6
as PCMCIA space.
0: Access physical space area 6 as ordinary memory
1: Access physical space area 6 as PCMCIA space
Notes: 1. Samples the value of the external pin (MD5) designating endian at power-on reset.
2. When selecting this mode, set the same bus width for areas 2 and 3.
3. Do not access to the SRAM when the clock ratio is I φ : B φ = 1:1.
8.4.2 Bus Control Register 2 (BCR2)
The bus control register 2 (BCR2) is a 16-bit read/write register that selects the bus-size width and
8-bit port of each area. It is initialized to H'3FF0 by a power-on reset, but is not initialized by a
manual reset or by standby mode. Do not access external memory outside area 0 until BCR2
register initialization is complete.
Bit
Bit Name
15, 14 —
13
A6SZ1
12
A6SZ0
Initial Value R/W Description
All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
1
R/W Area 6 Bus Size Specification
1
R/W Specify the bus sizes of physical space area 6.
• When port A/B is unused.
00: Reserved (Setting prohibited)
01: Byte (8-bit) size
10: Word (16-bit) size
11: Longword (32-bit) size
• When port A/B is used.
00: Reserved (Setting prohibited)
01: Byte (8-bit) size
10: Word (16-bit) size
11: Reserved (Setting prohibited)
Rev. 4.00, 03/04, page 172 of 660