HD6417706 Datasheet, PDF (10/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Item
2.4.1 Instruction Set
Classified by Function
Table 2.10 System Control
Instructions
Page
41 to
43
2.4.2 Instruction Code Map 45
Table 2.11 Instruction Code
Map
Revision (See Manual for Details)
Table 2.10 amended
Instruction
Operation
CLRMAC
0 → MACH, MACL
CLRS
0→S
CLRT
0→T
LDC Rm,SR
Rm → SR
LDC Rm,GBR
Rm → GBR
LDC Rm,VBR
Rm → VBR
LDC Rm,SSR
Rm → SSR
LDC Rm,SPC
Rm → SPC
LDC Rm,R0_BANK Rm → R0_BANK
LDC Rm,R1_BANK Rm → R1_BANK
LDC Rm,R2_BANK Rm → R2_BANK
LDC Rm,R3_BANK Rm → R3_BANK
LDC Rm,R4_BANK Rm → R4_BANK
LDC Rm,R5_BANK Rm → R5_BANK
LDC Rm,R6_BANK Rm → R6_BANK
LDC Rm,R7_BANK Rm → R7_BANK
LDC.L @Rm+,SR
(Rm) → SR, Rm + 4 → Rm
LDC.L @Rm+,GBR (Rm) → GBR, Rm + 4 → Rm
LDC.L @Rm+,VBR (Rm) → VBR, Rm + 4 → Rm
LDC.L @Rm+,SSR (Rm) → SSR, Rm + 4 → Rm
LDC.L @Rm+,SPC (Rm) → SPC, Rm + 4 → Rm
LDC.L @Rm+,
R0_BANK
(Rm) → R0_BANK,
Rm + 4 → Rm
LDC.L @Rm+,
R1_BANK
(Rm) → R1_BANK,
Rm + 4 → Rm
LDC.L @Rm+,
R2_BANK
(Rm) → R2_BANK,
Rm + 4 → Rm
LDC.L @Rm+,
R3_BANK
(Rm) → R3_BANK,
Rm + 4 → Rm
LDC.L @Rm+,
R4_BANK
(Rm) → R4_BANK,
Rm + 4 → Rm
LDC.L @Rm+,
R5_BANK
(Rm) → R5_BANK,
Rm + 4 → Rm
LDC.L @Rm+,
R6_BANK
(Rm) → R6_BANK,
Rm + 4 → Rm
LDC.L @Rm+,
R7_BANK
(Rm) → R7_BANK,
Rm + 4 → Rm
PREF @Rm
(Rm) → cache
STC.L SR,@–Rn
STC.L GBR,@–Rn
STC.L VBR,@–Rn
STC.L SSR,@–Rn
STC.L SPC,@–Rn
Rn–4 → Rn, SR → (Rn)
Rn–4 → Rn, GBR → (Rn)
Rn–4 → Rn, VBR → (Rn)
Rn–4 → Rn, SSR → (Rn)
Rn–4 → Rn, SPC → (Rn)
Code
0000000000101000
0000000001001000
0000000000001000
0100mmmm00001110
0100mmmm00011110
0100mmmm00101110
0100mmmm00111110
0100mmmm01001110
0100mmmm10001110
0100mmmm10011110
0100mmmm10101110
0100mmmm10111110
0100mmmm11001110
0100mmmm11011110
0100mmmm11101110
0100mmmm11111110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00110111
0100mmmm01000111
0100mmmm10000111
Privileged
Mode
—
—
—
√
—
√
√
√
√
√
√
√
√
√
√
√
√
—
√
√
√
√
Cycles T Bit
1
—
1
—
1
0
5
LSB
3
—
3
—
3
—
3
—
3
—
3
—
3
—
3
—
3
—
3
—
3
—
3
—
7
LSB
5
—
5
—
5
—
5
—
5
—
0100mmmm10010111 √
5
—
0100mmmm10100111 √
5
—
0100mmmm10110111 √
5
—
0100mmmm11000111 √
5
—
0100mmmm11010111 √
5
—
0100mmmm11100111 √
5
—
0100mmmm11110111 √
5
—
0000mmmm10000011 —
0100nnnn00000011 √
0100nnnn00010011 —
0100nnnn00100011 √
0100nnnn00110011 √
0100nnnn01000011 √
2
—
2
—
2
—
2
—
2
—
2
—
TRAPA #imm
PC → SPC, SR → SSR,
imm → TRA
11000011iiiiiiii —
8
—
Table 2.11 amended
Instruction Code
MSB
LSB
Fx: 0000
MD: 00
0000 Rn Fx 0000
0000 Rn Fx 0001
0000 Rn 00MD 0010 STC
SR,Rn
0000 Rn 01MD 0010 STC
SPC,Rn
0000 Rn 10MD 0010 STC
R0_BANK,Rn
0000 Rn 11MD 0010 STC
R4_BANK,Rn
0000 Rm 00MD 0011 BSRF Rm
0000 Rm 10MD 0011 PREF @Rm
0000 Rn Rm 01MD MOV.B Rm,@(R0,Rn)
Fx: 0001
MD: 01
STC GBR,Rn
STC
R1_BANK,Rn
STC
R5_BANK,Rn
MOV.W Rm,@(R0,Rn)
Fx: 0010
MD: 10
STC VBR,Rn
STC
STC
BRAF
R2_BANK,Rn
R6_BANK,Rn
Rm
MOV.L Rm,@(R0,Rn)
Fx: 0011 to 1111
MD: 11
STC SSR,Rn
STC
R3_BANK,Rn
STC
R7_BANK,Rn
MUL.L Rm,Rn
Rev. 4.00, 03/04, page x of xlvi