HD6417706 Datasheet, PDF (73/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

2.3.3 Instruction Formats
Table 2.3 explains the meaning of instruction formats and source and destination operands. The
meaning of the operands depends on the operation code. The following symbols are used.
xxxx: Operation code
mmmm: Source register
nnnn: Destination register
iiii:
Immediate data
dddd: Displacement
Table 2.3 Instruction Formats
Instruction Format
0 format 15
xxxx xxxx
xxxx
0
xxxx
Source
Operand
—
Destination
Operand
—
Instruction
Example
NOP
n format 15
xxxx nnnn xxxx
m
15
format
xxxx mmmm xxxx
0
xxxx
0
xxxx
—
Control register or
system register
Control register or
system register
mmmm: register
direct
mmmm: register
indirect with post-
increment
mmmm: register
indirect
mmmm: PC-
relative using Rm
nnnn: register MOVT
direct
Rn
nnnn: register STS
direct
MACH,Rn
nnnn: register STC.L
indirect with pre- SR,@–Rn
decrement
Control register LDC
or system
Rm,SR
register
Control register LDC.L
or system
@Rm+,SR
register
—
JMP
@Rm
—
BRAF
Rm
Rev. 4.00, 03/04, page 27 of 660