HD6417706 Datasheet, PDF (639/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
A25 to A16
A12 or A11
A15 to A0
Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 (Tpc) (Tpc)
t_AD
Row address
t_AD
t_AD
Row
address
;; _tAD
t_AD
Read command
t_AD
t_AD
Read A
command
t_AD
Row
address
;; ^tCSD3
Column address (1-4)
t_AD
t_CSD3
RD/
t_RWD
t_RASD ^tRASD
t_RWD
t_CASD
t_CASD
DQMxx
t_DQMD
D31 to D0
t_RDS2 t_RDH2
t_BSD
t_DQMD
t_RDS2 t_RDH2
t_BSD
CKE
DACKn
t_DAKD1
(High)
t_DAKD1
Figure 24.24 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read × 4), RCD = 0,
CAS Latency = 1, TPC = 1)
Rev. 4.00, 03/04, page 593 of 660