HD6417706 Datasheet, PDF (545/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

19.3.2 A/D Control/Status Register (ADCSR)
ADCSR is an 8-bit read/write register that selects the mode and controls the A/D converter.
Bit
Bit Name Initial Value R/W
Description
7
ADF
0
R/(W)*¹ A/D End Flag
Indicates the end of A/D conversion.
0: [Clearing conditions]
1. Cleared by reading ADF while ADF = 1, then
writing 0 in ADF
2. Cleared when DMAC is activated by ADI
interrupt and ADDR is read
1: [Setting conditions]
1. Single mode: A/D conversion ends
2. Multi mode: A/D conversion ends in all
selected channels
3. Scan mode: A/D conversion ends in all
selected channels.
6
ADIE
0
R/W
A/D Interrupt Enable
Enables or disables the interrupt (ADI) requested at
the end of A/D conversion. Set the ADIE when
convertion is stopped.
0: A/D end interrupt request (ADI) is disabled
1: A/D end interrupt request (ADI) is enabled
5
ADST
0
R/W
A/D Start
Starts or stops A/D conversion. The ADST bit
remains set to 1 during A/D conversion. It can also
be set to 1 by external trigger input at the ADTRG
pin.
0: A/D conversion is stopped
1: 1. Single mode: A/D conversion starts; ADST is
automatically cleared to 0 when conversion
ends.
2. Multi mode: A/D conversion stauts: ADST is
automatically cleard to 0 when conversion
ends in all selected channels.
3. Scan mode: A/D conversion starts and
continues, cycling among the selected
channels, until ADST is cleared to 0 by
software reset, or by a transition to standby
mode.
Rev. 4.00, 03/04, page 499 of 660