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| HD6417706 Datasheet, PDF (636/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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T1
Tw
Tw
TB2
TB1
TBw
T2
CKIO
tAD
A25 to A4
tAD
tAD
A3 to A0
tCSD1
CSn
RD/WR
RD
tRWD
tRSD
tAH
tCSD2 tRWH
tRSD1 tAH tRSD1
tRDH1
tRWD
tAH
tRSD tRWH
tRDS1
tRDH1
tRDS
tRDH1
D31 to D0
tBSD
tBSD
tBSD
tBSD
BS
tDAKD1
tDAKD2
DACKn
WAIT
tWTS tWTH
tWTS tWTH
tWTS tWTH
tWTS tWTH
Note: In the write cycle, the basec bus cycle is performed.
tRDH1: Stipulated from the faster negate timing of CSn or RD
tAH: Stipulated from the slower negate timing of CSn, RD, or WEn
Figure 24.21 Burst ROM Bus Cycle (External Wait)
Rev. 4.00, 03/04, page 590 of 660
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