HD6417706 Datasheet, PDF (275/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
T1
TB2
TB1
TB2
TB1
TB2
TB1
T2
A25 to A4
A3 to A0
RD/
D31 to D0
Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Figure 8.29 Burst ROM Basic Access Timing
8.5.6 PCMCIA Interface
In this LSI, setting the A5PCM bit in BCR1 to 1 makes the bus interface for physical space area 5
an IC memory card and I/O card interface as stipulated in JEIDA version 4.2 (PCMCIA2.1).
Setting the A6PCM bit to 1 makes the bus interface for physical space area 6 an IC memory card
and I/O card interface as stipulated in JEIDA version 4.2.
Figure 8.30 shows the PCMCIA space allocation.
When the PCMCIA interface is used, a bus size of 8 or 16 bits can be set by bits A5SZ1 and
A5SZ0, or A6SZ1 and A6SZ0, in BCR2.
Rev. 4.00, 03/04, page 229 of 660