HD6417706 Datasheet, PDF (323/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
1st sampling
2nd sampling is performed,
but since
is high,
per-cycle sampling starts
2nd sampling
3rd sampling is performed,
but since
is high,
per-cycle sampling starts
3rd sampling
DRAK
(High active)
Bus cycle
DACK
(RD output)
CPU
DMAC(Read)
DMAC(Write)
CPU
DMAC(Read)
DMAC(Write)
CPU
Figure 9.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed)
CKIO
1st sampling
2nd sampling is performed,
but since there is no ,4-3 falling edge,
per-cycle sampling starts
2nd sampling
3rd sampling is performed,
but since there is no ,4-3 falling edge,
per-cycle sampling starts
3rd sampling
,4-3
DRAK
(High active)
Bus cycle
CPU
High High
DMAC(Read)
DMAC(Write)
CPU
High High
DMAC(Read)
DMAC(Write)
CPU
DACK
(RD output)
Note: When a ,4-3 falling edge is detected, ,4-3 must be high for at least one cycle before the sampling point.
Figure 9.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles)
1st sampling
CKIO
2nd sampling
3rd sampling
DRAK
(High active)
Bus cycle
DACK
CPU
DMAC(Read)
DMAC(Write)
DMAC(Read)
DMAC(Write)
DMAC(Read)
Figure 9.22 Burst Mode, Level Input
Rev. 4.00, 03/04, page 277 of 660