HD6417706 Datasheet, PDF (425/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Receiving Serial Data (Asynchronous Mode): Figure 14.10 shows a sample flowchart for
receiving serial data. Serial data reception should be carried out in the following procedure after
setting the SCI in a reception-enabled state.
Start reception
Read ORER, PER, and FER
bits in SCSSR
PER = 1,
FER = 1,
Yes
or ORER = 1?
No
Read the RDRF bit in SCSSR
Error processing
No
RDRF = 1?
Yes
Read reception data of SCRDR
and clear RDRF bit in SCSSR to 0
No
All data received?
Yes
Clear the RE bit in SCSCR to 0
End reception
1. Receive error processing and break
detection: If a receive error occurs,
read the ORER, PER and FER bits
of the SCSSR to identify the error.
After executing the necessary error
processing, clear ORER, PER and
FER all to 0. Receiving cannot
resume if ORER, PER or FER remain
set to 1. When a framing error occurs,
the RxD0 pin can be read to detect the
break state.
2. SCI status check and receive-data read:
Read the SCSSR, check that RDRF is
set to 1, then read receive data from the
SCRDR and clear RDRF to 0. The RXI
interrupt can also be used to determine
if the RDRF bit has changed from 0 to 1.
3. To continue receiving serial data: Clear
RDRF to 0 before the stop bit of the
current frame is received.
Figure 14.10 Sample Flowchart for Receiving Serial Data
Rev. 4.00, 03/04, page 379 of 660