HD6417706 Datasheet, PDF (468/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Module data bus
Internal
data bus
SCFRDR2
(16 stages)
SCFTDR2
(16 stages)
RxD2
TxD2
SCK2
SCRSR2
SCTSR2
Parity generation
Parity check
Legend
SCRSR2:
SCFRDR2:
SCTSR2:
SCFTDR2:
SCSMR2:
SCSCR2:
Receive shift register 2
Receive FIFO data register 2
Transmit shift register 2
Transmit FIFO data register 2
Serial mode register 2
Serial control register 2
SCPCR
SCPDR
SCFDR2
SCFCR2
SCSSR2
SCSCR2
SCSMR2
Transmit/
receive
control
SCBRR2
Baud rate
generator
Clock
Pφ
Pφ/4
Pφ/16
Pφ/64
External clock
SCIF
TEI
TXI
RXI
BVRI
SCSSR2:
SCBRR2:
SCFCR2:
SCFDR2:
SCPDR:
SCPCR:
Serial status register 2
Bit rate register 2
FIFO control register 2
Number of FIFO data register 2
Port SC data register
Port SC control register
Figure 16.1 SCIF Block Diagram
Rev. 4.00, 03/04, page 422 of 660