HD6417706 Datasheet, PDF (526/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit
Bit Name
Initial Value R/W
Description
7
PA7DT
0
R/W
Table 18.1 shows the function of PADR.
6
PA6DT
0
R/W
5
PA5DT
0
R/W
4
PA4DT
0
R/W
3
PA3DT
0
R/W
2
PA2DT
0
R/W
1
PA1DT
0
R/W
0
PA0DT
0
R/W
Table 18.1 Read/Write Operation of the Port A Data Register (PADR)
PAnMD1 PAnMD0 Pin State
Read
Write
0
0
Other function PADR value Value is written to PADR, but does not affect
pin state.
1
Output
PADR value Write value is output from pin.
1
0
Input (Pull-up Pin state
MOS on)
Value is written to PADR, but does not affect
pin state.
1
Input (Pull-up Pin state
Value is written to PADR, but does not affect
MOS off)
pin state.
(n = 0 to 7)
18.2 Port B
Port B is an 8-bit I/O port with the pin configuration shown in figure 18.2. Each pin has an input
pull-up MOS, which is controlled by Port B Control Register (PBCR) in PFC.
Port B
PTB7 (I/O) / D31 (I/O)
PTB6 (I/O) / D30 (I/O)
PTB5 (I/O) / D29 (I/O)
PTB4 (I/O) / D28 (I/O)
PTB3 (I/O) / D27 (I/O)
PTB2 (I/O) / D26 (I/O)
PTB1 (I/O) / D25 (I/O)
PTB0 (I/O) / D24 (I/O)
Figure 18.2 Port B
Rev. 4.00, 03/04, page 480 of 660