HD6417706 Datasheet, PDF (625/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Stable input clock
EXTAL input
or CKIO input
PLL synchronization
PLL output,
CKIO output
Internal clock
IRQ4 to IRQ0/ to
interrupt request
Stable input clock
t_IRLSTB
t_PLL1
PLL synchronization
STATUS 0
STATUS 1
Normal
Standby
Normal
Note: Oscillation settling time in the Clock-mode-0, 1, 7 and Oscillation-halt-mode
Figure 24.9 PLL Synchronization Settling Time
at the returning from Standby mode (Return by IRQ/IRL Interrupt)
Multiplication rate modified
EXTAL input*¹
PLL output,
CKIO output*²
Internal clock
t_PLL2
Notes: 1. CKIO input in clock mode 7
2. PLL output in clock mode 7
Figure 24.10 PLL Synchronization Settling Time when Frequency Multiplication
Rate Modified
Rev. 4.00, 03/04, page 579 of 660