HD6417706 Datasheet, PDF (525/709 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section 18 I/O Ports
This LSI has 10 ports (ports A to J and SC). All port pins are multiplexed with other pin functions
(Pin Function Controller (PFC) maintains the selection of the pin functions and pull-up MOS
control). Each port has a data register which stores the data to the pins.
18.1 Port A
Port A is an 8-bit I/O port with the pin configuration shown in figure 18.1. Each pin has an input
pull-up MOS, which is controlled by Port A Control Register (PACR) in PFC.
Port A
PTA7 (I/O) / D23 (I/O)
PTA6 (I/O) / D22 (I/O)
PTA5 (I/O) / D21 (I/O)
PTA4 (I/O) / D20 (I/O)
PTA3 (I/O) / D19 (I/O)
PTA2 (I/O) / D18 (I/O)
PTA1 (I/O) / D17 (I/O)
PTA0 (I/O) / D16 (I/O)
Figure 18.1 Port A
18.1.1 Register Description
Port A has the following register. Refer to section 23, List of Registers, for more details of the
addresses and access sizes.
• Port A data register (PADR)
18.1.2 Port A Data Register (PADR)
Port A data Register (PADR) is an 8-bit read/write register that stores data for pins PTA7 to
PTA0. PA7DT to PA0DT bit corresponds to PTA7 to PTA0 pin. When the pin function is general
output port, if the port is read the value of the corresponding PADR bit is returned directly. When
the function is general input port, if the port is read the corresponding pin level is read.
Rev. 4.00, 03/04, page 479 of 660